How to setup dependencies in Makefile for C/C++ program?

I am writting a C program in Linux using GNU and Makefile.
Now I want to do something before building the codes in Makfile.

CSRCS += a.c
CSRCS += b.c
CSRCS += x.c

object=$(patsubst %.c,%.o,$(CSRCS))

TARGET = $(addprefix $(BUILD_OBJ_DIR)/, $(patsubst ./%, %, $(object)))

all: before_build default ## <<<<

$(BUILD_OBJ_DIR)/%.o: %.c
        mkdir -p $(dir $@)
        $(CC)  $(CFLAGS) -c $< -o $@
        echo "CC $<"

before_build:
        echo "Doing something before build"
default: $(TARGET)
        @mkdir -p $(dir $(BUILD_BIN_DIR)/)
        $(CC) $(CFLAGS) -o $(BUILD_BIN_DIR) $(TARGET)

clean:
        rm -rf $(BUILD_DIR)

I wrote all: before_build default, hoping make all will run target of before_build to do something before really compiling the codes.

But I found make all did NOT run before_build, why? And how to create dependencies in Makefile?